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Power calculation for low power design in SOC
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- Category: ASIC - Backend
- Written by Harsh
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Posted by Krishna c
Hi friends…,
Today in a discussion I happend to hear that some time some of
the blocks in a SOC are switched off when not in use.
Let me explain with an example.
In a Transiever. Sometimes it happens in such a way that when transmission
is occuring the reciever may be switched off as there is no use with the
reciever except count the clock. So during this time the reciever is
switched off in an SoC. that is no power is supplied to that particular
circuit.
My doubts now are ::
1 How is the power calculated for this kind of circuits?
2. How will the circuit go to power mode?(what kind circuitary is added in
order to achieve this?)
3. How much is it feasible to switch off the whole circuit?
eply to above by Kiran
See answers bwlow questions–
I have doubt, today in a discussion I happen to hear that some time some of the blocks in a SOC are switched off when not in use.
Let me explain with an example.
In a Transiever. Sometimes it happens in such a way that when transmission is occuring the reciever may be switched off as there is no use with the reciever except count the clock. So during this time the reciever is switched off in an SoC. that is no power is supplied to that particular circuit.
My doubt now are ::
1 How is the power calculated for this kind of circuits?
You know power consumption of blocks from front end itself i.e by power compiler. With this u can plan at RTL level only such that some logic may be switched off .
2. How will the circuit go to power mode?(what kind circuitary is added in order to achieve this?)
a) Some designers use clock gating.This clock gating can be done to bunch of registers,a module or even to a block also in a soc.
b)Some designers use Voltage Islands.i.e multiple voltages in a single design.They just switchoff that particular voltage such that the
logic operating with this voltage will not operate.
3. How much is it feasible to switch off the whole circuit?
Question not clear
Hi Kiran,
My 3rd Question was is when we switch off and on, many registers get
resetted so in that way how are we restoring the previous data. In case if
we are restoring the data the restoring itself takes much time so how
feasible is it to manage this??
Doubts is 2nd Answer. How can one switch off some nets. Is it done at the
pad level or the power rail level or is there anything else managing this.
Please elaborate what voltage islands and a general architecture of volatage
Islands.. It will be useful if U send some material with respect to this. I
searched for that but cud not find that.
in 2nd (a) answer U explained abt clock gating but I am talking abt totally
switching the circuit.
Reply posted by vinodh–
In single SOC some region of logic operates with one voltage say VDD1, another SOC region with VDD2. Like this you can have many voltage regions. (This is multiple voltage islands)
Power consumption is directly proportional to applied voltage. Second point speed of the circuit is also directly proportional to applied voltage.
To reduce power consumption you reduce applied voltage (this is one technique), but because of this circuit speed will come down.
That’s why in single SOC, the regions (you can say blocks or modules) which need not operate with high speed can be applied with low voltage. Vice-versa (high speed circuits with high voltage). This forms multiple voltage regions in single SOC. This way you can reduce power and same time you can achieve timing also.
Reply by Kiran –
Regarding u r 3rd question,in the designs with voltage islands different Voltages are handled in a speiclized manner.There was a specialized mechanism in switching off some blocks and again switching on those blocks again.i will let u kow about this.
Regardig nd question,let us assume u have 10 blocks in an SOC. U want to
switch off Block completely. And say BLOCK1 had communiation with BLOCK2 and BLOCK3.
During RTL itself u decide if u switch of BLOCK1 then is there any effect o other communicating blocks.Moreover the concept of switching off some logic
comes into picture when its effect on other logic is ot there
Regarding Second Question:
There are certain power managment cells which control this activity which are called switch cells. which manages with the outputs from the switched off net not to go hig impedence or floating states as it has no defined state. This will make sure the circuit to work in power off mode.
These are mostly the analog cells and does not coming into the timing paths.
Regards…,
Krishna C