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Interview questions VLSI frontend

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Category: ASIC
Written by Harsh
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Hey,

I am sure a lot of you have changed jobs etc and attended interviews. I would like you to post some of the questions that were asked in interviews for Coding/ Verification engineers.

This ought to help with future interviews

 

  1. Are you familiar with the term MESI?
  2. Are you familiar with the term snooping?
  3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
  4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
  5. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
  6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
  7. Explain the operation considering a two processor computer system with a cache for each processor.
  8. What are the main issues associated with multiprocessor caches and how might you solve it?
  9. Explain the difference between write through and write back cache.
  10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++?
  11. Have you studied busses? What types?
  12. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
  13. How many bit combinations are there in a byte?
  14. What is the difference between = and == in C?
  15. When will you use a latch and a flipflop in a sequential design?
  16. Design a 1-bit fulladder using a decoder and 2 “or” gates?
  17. You have a circuit operating at 20 MHz and 5 volt supply. What would you do to reduce the power consumption in the circuit- reduce the operating frequency of 20Mhz or reduce the power supply of 5Volts and why?
  18. In a SRAM circuit, how do you design the precharge and how do you size it?
  19. In a PLL, what elements(like XOR gates or Flipflops) can be used to design the phase detector?
  20. Give two ways of converting a two input NAND gate to an inverter
  21. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
  22. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
  23. Give a circuit to divide frequency of clock cycle by two
  24. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
  25. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
  26. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied?
  27. Give the truth table for a Half Adder. Give a gate level implementation of the same.
  28. Draw a Transmission Gate-based D-Latch.
  29. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
  30. How do you detect if two 8-bit signals are same?
  31. How do you detect a sequence of “1101″ arriving serially from a signal line?
  32. Design any FSM in VHDL or Verilog

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