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Random number in Verilog
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- Details
- Category: ASIC
- Written by Harsh
- Hits: 296
Verilog as two functions to generate a random number -
$dist_uniform and $random
Usage:
$dist_uniform(seed, min, max)
min + {$random(seed)}%(max-min+1)
It seems like there is no difference in distribution. For both functions, distribution is uniform. Both functions follows the same distribution rule, but generate different pseudo-random sequences for the same seed value. So essentially these two functions have two different polynomial equations which generate equally random numbers.